Analysis of Technology Mapping Algorithm for Logic optimization of Symmetrical FPGA Architecture through Hybrid LUTs/PLAs

Reconfigurable computing using Field Programmable Devices (FPD) provides a method to utilize the available logic resources on the chip for various computations. The basic ability of reconfigurable computing is to perform computations in hardware to increase performance, while retaining the flexibility of application software. The purpose of this paper is to analysis the effect of technology mapping algorithms on logic density of FPGA devices for reconfigurable computing system using Hybrids of Look up tables (LUTs) from FPGA and Programmable logic arrays (PLAs) from CPLD architectures. LUTs/PLAs are both contributing particular strengths in the area of reconfigurable system design. We identified Hybrid LUTs/PLAs architectures as Hybrid Reconfigurable Computing Architectures (HRCA). The basis of the HRCA is that some parts of digital circuits are well-suited for execution with LUTs, but other for PLAs structures. The technology mapping step converts the user define gate level network into a network of LUTs. We evaluate the extensive comparison of technology mapping algorithms over 20 MCNC benchmark circuits from a common application ported on the given circuit by using the following algorithms, chortle-d, mispga-delay, FlowMap, and DAG-Map. The primary objective of this paper to find suitable optimal mapping algorithm in terms of logic density minimization with respect to reduce the number of KLUT’s used in the technology mapping solution. It also offers some improvements in computation speedup and power consumption. Initially results indicate that noteworthy logic area of symmetrical FPGA is reduced by using flow Map technology mapping algorithm on