Analysis of Aps Readout Circuit Delay

ABSTRACT The paper provides a complete analysis of the APS pixel and column circuit delay. Contrary to common belief, we show that shorter settling times can be achieved by reducing the bias current and hence reducing energy consumption. We then investigate the effect of non-idealities on the readout operation. We find that when the follower transistor channel length modulation is taken into consideration, delay is reduced, which implies that shorter length transistors can be used in the pixel. As expected, we find that delay decreases linearly with technology scaling.