A Frequency Synthesizer for Wireless LAN 802.11a and 802.11b Multi-Standard Transceiver

A BiCMOS frequency synthesizer compliant for both Wireless LAN (WLAN) 802.11a and 802.11b standards is presented. Proposed adaptive dual-loop PLL architecture improves reference spur rejection and settling time performance. The synthesizer is fabricated in a 0.25 μm BiCMOS process and dissipates 70 mW from a single 2.5 V supply. It occupies a silicon area of 1.7 mm2. Test-chip measurement results show −56 dBc reference spurs at a frequency offset of 2 MHz, while maintaining a settling time close to 80 μs. Description 1. System Architecture Narrow loop bandwidth is particulary useful to reject reference spurs. System level simulation results show that the reference spur must be at least 36 dB below the carrier signal to keep a BER better than 10−5 when the input SNR is 11.5 dB. However, if the bandwidth is too narrow, the loop time constant becomes too slow to meet the settling time requirement. The problem of slow settling time can be avoided by utilizing the adaptive dual-loop PLL (ADPLL) as a speedup method. The fundamental idea of the adaptive dual-loop PLL is shown in Fig. 1. When the loop is stable, and thus the phase error small, only the main loop is active and the synthesizer operates with a narrow loop bandwidth. When the phase error becomes large due to a frequency step in the feedback path, the auxiliary path becomes active and pushes the loop bandwidth to a higher frequency. Once the output signal is close enough to the target frequency, the loop bandwidth returns to its original value so that any spurious signal is rejected. Fig. 1(b) shows the actual locations of poles and zeros for this implementation. Loop bandwidth is kept narrow at 9.3 kHz during the steady state and is pushed to 42 kHz for faster settling during the transition state. PFD1 CP1 Loop Filter PFD2 CP2