An optimized Direct Digital Frequency Synthesizer (DDFS)
نویسندگان
چکیده
An optimized Direct Digital Frequency Synthesizer (DDFS) design in terms of reduced ROM, high throughput and speed is designed in this paper. DDFS is designed with 200 MHz reference clock frequency and 32 bit FTW for the generation of sine and cosine signal with 16 bit output frequency having frequency resolution of 0.0466 Hz and Phase resolution of 0.0055°. DDFS design is simulated using VHDL in ModelSim 10.1d and then synthesized using Xilinx ISE 13.2 tool for implementation in FPGA-Spartan3E. The performance of designed Reduced ROM based DDFS shows that the latency of normal ROM based DDFS is improved by 369 ns. Through CORDIC algorithm, the Reduced DDFS is further improved by increasing its maximum frequency to 138.47 M Hz with latency of 73 ns and reducing its number of slices and LUTs by 56 %.
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