Energy Consumption in Embedded Systems

2 0740-7475/04/$20.00 © 2004 IEEE Copublished by the IEEE CS and the IEEE CASS IEEE Design & Test of Computers ALONG WITH SPEED AND COST, energy consumption is now a primary performance metric for battery-operated embedded systems. A well-designed embedded system should be globally optimized to the target application, from the user interface to the device technology. This type of global optimization over many layers of software and hardware is challenging because most designs require extensive interdisciplinary collaboration. Energy estimation is routine in low-level hardware design. Unfortunately, at this stage, the specific application of most hardware components is unknown, and designers can’t perform an application-specific optimization. Another opportunity for optimization is during software and systems design, but these designers are often unfamiliar with hardware-related energy issues. This problem is compounded because traditional energy estimation tools such as Spice and PowerMill target low-level-hardware engineers, which might discourage designers working at higher levels from attempting global optimization. A simple approach is to analyze actual measurements from a hardware platform. Tools such as Itsy use computer-controlled multimeters or A/D converters to measure energy consumption.1 However, although these measurement-based systems are not restricted to a specific target, they have certain limitations. The major drawback of Itsy is that it is incapable of performing cycle-accurate analysis because it averages energy consumption over the entire execution time. Other studies adopt a software energy estimation methodology—an important aspect of embedded-systems design since Tiwari, Malik, and Wolfe first introduced this methodology.2 Their work focused on the possibility of software optimization, but recently proposed tools extend the methodology to support highlevel hardware optimization. For example, JouleTrack is a publicly available Web-based software energy-profiling tool for processor cores.3 SimplePower and Wattch estimate the power consumption of processors, including the on-chip cache, on-chip bus, and on-chip SRAM, but still excluding the off-chip subsystems.4,5 JouleTrack, SimplePower, and Wattch are suitable for architecturelevel analysis because they consider only processors. On the other hand, Simunic, Benini, and De Micheli present a system-level energy estimation framework that includes a processor, an L1/L2 cache, off-chip memory, and a DC-DC converter.6 Nevertheless, energy models for off-chip memory devices are too simple to support a cycle-level analysis. Their framework takes a basic power-per-mode approach and assumes that devices have only two modes: active and idle. The increasing trend toward low-power design requires a higher-fidelity, system-level energy estimation environment. Here, we propose a Web-based energy exploration tool, the SNU (Seoul National University) Energy Explorer (SEE) Web—the publicly promoted verWeb-Based Energy Exploration Tool for Embedded Systems