Formal Validation and Verification of Networks-on-Chips: Status and Perspective

Increasing the performance of computing system today means more parallelism. Systems are becoming multi-cores. The on-chip interconnect is a complex infrastructure having a crucial impact on the system global performance and functionality. In this draft paper we present recent results and work-in-progress towards a general compositional approach for the validation and verification of networks-on-chips. In particular, we discuss temporal abstractions, a refinement theorem between two architectures described at the same temporal abstraction, and two properties – namely deadlock and evacuation – proven on a model defined at a more abstract temporal layer.