Veri cation of VLSI Circuits: Signal Value Modeling and HDL Translation

The ever increasingly number of transistors possible in VLSI circuits compounds the diiculty in ensuring correct designs. Formal veriication has been touted as a means of overcoming this problem, but most of the work in this area has been directed at standalone theorem provers. Before veriication is accepted by the VLSI design community, the stand alone veriication tools that are in use in the research community must be integrated with the CAD tools used by designers. The primary obstacle is that the hardware description languages (HDL's) used in veriication tools are often not syntactically or semantically compatible with the hardware description languages commonly used in the VLSI design community. The research presented in this paper is directed at this problem. We have built a parser for the BOLT hardware description language in the HOL theorem proving system. This provides a means of using the same language in the theorem proving system and the VLSI CAD tools used in our work. We have also built a semantic model in HOL for the signal values used in the simulator in our CAD tool suite. We show how this semantic model can be used for reasoning about the signal value data types that are used in the BOLT hardware description language and the VHDL Standard Logic Package.