Power-Efficient Con- tinuous-Time Incre- mental Sigma-Delta Analog-to-Digital Con- verters

Time-Mode Signal Quantization for Use in Sigma-Delta Modulators

The rapid scaling in modern CMOS technology has motivated the researchers to design new analog-to-digital converter (ADC) architectures that can properly work in lower supply voltage. An exchanging the data quantization procedure from the amplitude to the time domain, can be a promising alternative well adapt with the technology scaling. This paper is going to review the recent development in t...

An 8-bit Low-Power ADC Array for CMOS Image Sensors

!BSTRACT  4HE PAPER PRESENTS AN ORIGINAL ANALOG TO DIGITAL CONVERTER !$# ARRAY MEETING THE CON STRAINING REQUIREMENTS IN RESOLUTION SPEED SIZE AND LOW POWER CONSUMPTION OF HIGH PERFORMANCE LOW COST VIDEO CAMERAS 4HE CONVERTER ARRAY IS BASED ON !$# CELLS RELYING ON A CYCLIC REDUNDANT SIGNED DIGIT 23$ ALGORITHM SUPPORTING COMPARATORS WITH EXTENDED TOLERANCE ! PROTOTYPE !$# ARRAY COMPOSED OF CON ...

Power Efficient Continuous-Time Delta-Sigma Modulator Architectures for Wideband Analog to Digital Conversion

Design of A high performance low-power consumption discrete time Second order Sigma-Delta modulator used for Analog to Digital Converter

This paper presents the design and simulations results of a switched-capacitor discrete time Second order Sigma-Delta modulator used for a resolution of 14 bits Sigma-Delta analog to digital converter. The use of operational amplifier is necessary for low power consumption, it is designed to provide large bandwidth and moderate DC gain. With 0.35μm CMOS technology, the ΣΔ modulator achieves 86 ...

Decrease in Hardware Consumption and Quantization Noise of Digital Delta-Sigma Modulators and Implementation by VHDL

A new structure is presented for digital delta-sigma modulator (DDSM). Novel architecture decreases hardware consumption, output quantization noise and spurs in Comparison to previous architectures. In order to reduce the delay, power consumption and increase maximum working frequency, the pipelining technique and the carry skip adder are used. Simulation proposed architecture shows that the qu...