A multi-pipeline architecture for high-speed packet classification

When a packet arrives at a flow-aware router, it is subject to a number of lookup and classification operations. The packet is first checked against an access control list and/or firewall to determine whether it will be accepted or rejected. This classification function supports packet filtering and provides IPSec security associations. A second classification is used to regulate the traffic on a per-flow basis. This step supports quality-of-service provisioning, traffic shaping, and billing and accounting. Packet classification uses multiple TCP/IP header fields to classify packets into flows. A typical classification rule involves five TCP/IP header fields, namely the source and destination IP address (SA, DA), the source and destination port number (SP, DP), and the protocol (PT) field. A novel multi-pipeline architecture for packet classification is presented in this talk. The method has outstanding performance in both space and time. We incorporate the prefix inclusion coding scheme to achieve outstanding memory efficiency. The hardware uses fixed-length linear pipelines. Hence, the classification rate is constant regardless of the ruleset properties. The proposed architecture is implemented on a Vertex-6 FPGA and the device can achieve a classification rate of 340 million packets per second. Brief Biography Miss Ziyan Lu received the Bachelor of Engineering in Electronic Engineering and Information Science at University of Science and Technology of China in 2009. Now she is working towards the Doctor of Philosophy in Electronic Engineering at City University of Hong Kong. Her current research interest is IP address lookup and packet classification. ** All are welcome **