A New Design of Multiplier using Modified Booth Algorithm and Reversible Gate Logic

In this paper we propose a new concept for multiplication by using modified booth algorithm and reversible logic functions. Modified booth algorithm produces less delay compare to normal multiplication process. Modified booth algorithm reduces the number partial products which will reduces maximum delay count a the output. by combining modified booth algorithm with reversible gate logic it will produces further less delay compare to all other. In the past years reversible logic functions has developed as an important research area. Implementing reversible logic has the advantage of reducing the gate count, garbage outputs as well as constant inputs. Addition subtraction operations are realized using reversible DKG gate. This modified booth algorithm with reversible gate logic are synthesized and simulated by using Xilinx 13.2 ISE simulator.