Conditional Partial Order Graphs

This work presents a new formal model for specification and synthesis of microcontrol circuits. The model, called Conditional Partial Order Graph, captures concurrency and choice in a system’s behaviour in a compact and efficient way. It is especially beneficial for a class of systems which have many behavioural scenarios defined on the same set of primitive events or actions, e.g. CPU microcontrollers. The key feature of the model is its ability to specify systems in a compact functional form as opposed to the existing models which either have a direct event traces representation or use an explicit notion of states and transitions between the states. In this approach a system is specified with a set of scenarios, each of them being a partial order of events. The scenarios are further composed into a single graph containing all the partial orders in a functional form. This superposition is obtained by assignment of Boolean conditions to the events and dependencies between them, hence the name of the model. As a result the specification has different levels of abstraction for control and data paths: control flow is represented with partial orders of events, while data path is modelled at the level of Boolean functions. Such separation helps to avoid exponential explosion in the size of system specification which happens in other models. At the stage of microcontroller synthesis the obtained graph is structurally mapped into logic equations without the explicit exploration of the system state space, thereby leading to algorithms with high time and memory efficiency. The model has potential applications in the area of microcontrol synthesis and brings new methods for modelling concurrency into the domain of modern and future processor architectures. Several application examples are presented, namely basic handshake components and processor microcontrollers, as well as phase encoding circuits used in digital communication channels. As a result of this work several synthesis, verification, optimisation and mapping tools have been developed to facilitate specification and synthesis of microcontrollers using the proposed methodology. The tools have been successfully incorporated into the WORKCRAFT framework for visualisation and simulation support.