A high-performance two-stage packet switch architecture

نویسنده

  • Timothy X. Brown
چکیده

This paper contributes a distributed packet controller which reduces queueing to a single stage in two-stage packet switches. Software and neural network based controllers are described. Simulations under a range of traffic conditions for a 1024x1024 switch size shows the simplest architecture has the best performance.

برای دانلود رایگان متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

Design of Arrayed Waveguide Grating based Optical Switch for High Speed Optical Networks

This paper demonstrates the design of an Arrayed Waveguide Gratings (AWG) based optical switch. In the design both physical and network layer analysis is performed. The physical layer power and noise analysis is done to obtain Bit Error Rate (BER). This has been found that at the higher bit rates, BER is not affected with number of buffer modules. Network layer analysis is done to obtain perfor...

متن کامل

Design and Analysis of a Fully-Distributed Parallel Packet Switch with Buffered Demultiplexers

A Parallel Packet Switch (PPS) is a multistage switch aimed at building a very high-speed switch using much slower devices. A PPS in general has three stages. Several packet switches are placed in the central stage, which operate slower than the external line’s rate. Incoming packets are spread over the center-stage switches by demultiplexers at the input stage. Packets destined to each output ...

متن کامل

Clos-knockout: a Large-scale Modular Multicast Atm Switch

A large-scale modular multicast ATM switch based on a three-stage Clos network architecture is proposed and its performance is studied in this paper. The complexity of our proposed switch is N p N if the switch size is N N. The rst stage of the proposed multicast switch consists of n sorting modules, where n = p N. Each sorting module has n inputs and n outputs and is responsible for traac dist...

متن کامل

Scheduling Algorithm with Consideration to Void Space Reduction in Photonic Packet Switch

In this paper, we comparatively evaluate two photonic packet switch architectures with WDM-FDL buffers for synchronized variable length packets. The first one is an output buffer type switch, which stores packets in the FDL buffer attached to each output port. Another is a shared buffer type switch, which stores packets in the shared FDL buffer. The performance of a switch is greatly influenced...

متن کامل

Scheduling Algorithm with Void Space Reduction in Photonic Packet Switch

In this paper, we comparatively evaluate two photonic packet switch architectures with WDM-FDL buffers for synchronized variable length packets. The first one is an output buffer type switch, which stores packets in the FDL buffer attached to each output port. Another is a shared buffer type switch, which stores packets in the shared FDL buffer. The performance of a switch is greatly influenced...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

عنوان ژورنال:
  • IEEE Trans. Communications

دوره 47  شماره 

صفحات  -

تاریخ انتشار 1999