A longitudinal study of Arithmetic logic unit and floating point unit performance, structure, and design

The Past fifteen years have seen an extraordinary increase in ALU and floating point unit technology, from space efficiency to power management. In order to quantify some of these changes, several research papers authored over a decade and a half were collected for study and analysis. Measurements of interest included Power consumption of ALU, ITRS technology node width, Execution time per ALU, and Data bus width. Notable designs that stand out for each time period studied include the sub 500ps 64 bit ALU in .18 um CMOS [18] for the earlier period covered in this paper, where we see a design rather advanced for its time. As time progresses, we see more powerful and more efficient hardware such as the Ultraarea-efficient fault-tolerant QCA full adder [2], which demonstrates the advancements made over the past fifteen years in power efficiency and execution time. Keywords— Bus Width, ALU, Bit Shift Hardware, Instruction, Overflow, Register, Multiplexer, ITRS