A Genetic Algorithm Based Approach For Optimization Of Test Time And TAM Length For 3D SoC Considering Pre-Bond Test Under The Constraint On The Number Of TSVs

Core-based system-on-chips (SoCs) fabricated on three-dimensional (3D) technology are emerging for better integration capabilities. Effective test architecture design and optimization techniques are essential to minimize the manufacturing cost for such gigascale integrated circuits. Test-access mechanisms (TAMs) and test wrappers (e.g., the IEEE Standard 1500 wrapper) facilitate the modular testing of embedded cores in a corebased system-on-chip (SoC). Such a modular testing approach can also be used for emerging three-dimensional integrated circuits based on through-silicon vias (TSVs).This paper presents a Genetic algorithm(GA) based solution to Cooptimize test scheduling and TAM length for 3D SoC. A locally optimal best-fit heuristic based bin packing algorithm has been used to determine placement of cores minimizing the overall routing cost. Experimental result on ITC'02 benchmark SoCs shows that the proposed method provides few better test time results compared to earlier work.