Data Cache Performance When Vector-Like Accesses Bypass the Cache

A Stream Memory Controller, when added to a conventional memory hierarchy, routes vector-like accesses around the data cache. A memory system was simulated under these conditions and the data cache performance increased dramatically. The gain in performance was a result of the increased temporal locality of the access pattern. The access pattern also showed a decrease in spatial locality, making smaller cache lines nearly as effective as long ones. This research attempts to quantify the effect on the data cache when vector-like accesses are handled outside the cache system. We hypothesized that vector-like accesses took up large amounts of space in the cache, had poor temporal locality, and, therefore, would cause cache pollution. In the primary experiments, we removed the vector-like accesses from the cache system and saw cache performance increase. Additional experiments , which examined the causes of the increase in cache performance, provided evidence to support our hypothesis We wanted to examine a memory system where vector-like accesses bypass the cache because our research group has designed a piece of hardware called the Stream Memory Controller (SMC) [7,9] which can increase the speed of vector-like memory accesses which go directly to DRAM. Since previous research [8] had studied the effect of the SMC on the vector-like data, we needed to simulate the memory system where the