Optimization of 22 nm Logic Gates for Power-and-Noise-Margin and Energy-and-Noise-Margin

In this paper, we propose a technique for concurrent optimization of CMOS logic gates for power-and-noisemargin and energy-and-noise-margin. The role of progressive sizing for performance enhancement of different gates has been expanded to cover other figures of merit, such as reliability, power, and energy. By using the examples of threeand four-input logic gates, we have demonstrated how multiple, yet conflicting design goals can be achieved. For example, one of our high-performance gates exhibited power savings of more than 30% while reducing the gate area by 39%. An important step of balancing the riseand fall-times of output was also incorporated into the optimization setup. Our proposed methodology is scalable and can be used for optimizing larger logic blocks.