Design of Bufferless On-Chip Routers Providing In-Order Packet Delivery

Previous bufferless router designs require to drop and retransmit packets or deflect them each time a network channel get conflicted. These approaches, unfortunately, make data packets and even their flits arrive at destinations out-of-order. In this work, we present a new bufferless router architecture that provides in-order packet delivery. The key idea is to utilize pipeline registers at channel links as storage elements that allow the router to operate as a wormhole router without physical buffers. The router employs a dimension-ordered deterministic routing policy without packet dropping. To obtain higher performance, we also propose a new flow control technique called Express Flow Control (EFC) that allows all flits of an in-flight packet to synchronously forward each time its head flit wins the output port arbitration. Experimental results show that both proposed router architectures guarantee in-order packet delivery. BufferlessEFC routers are 23% less latency and 60% greater throughput than bufferless routers while have 2.5% smaller area and 4.7% lower power.