Compiled Code Acceleration Of NAMD On FPGAs
نویسندگان
چکیده
Spatial computing, as implemented on reconfigurable platforms, such as FPGAs, presents an effective solution to high performance computing applications where computations are applied repeatedly to streams of data. Bridging the gap between program descriptions and hardware system implementations, however, is a challenging problem. ROCCC is a C/C++ to VHDL compiler that focuses on extensive loop, array and procedure code transformations. In this paper we report on using ROCCC to compile NAMD, a modern and popular molecular dynamics program, and executing it on the SGI Altix 4700 with a RASC blade. The critical region of NAMD is a loop nest that computes the non-bonded forces on the atoms in a molecule. An instance of this loop consists of 52 floating point operations performed on several input arrays. Using ROCCC, this loop was translated to VHDL and then mapped onto the Virtex 4 LX200 of the RASC blade. Our results show a speedup exceeding 800x over a 1.6 GHz Itanium processor with a potential sustained rate of 7.7 Gflops on the FPGA for a single precision floating point
منابع مشابه
Compiled Code Acceleration on Fpgas
The ROCCC (Riverside Optimizing Configurable Computing Compiler) is an optimizing C-to-VHDL compiler used to compile routines written in a subset of C to an application-specific circuit on an FPGA. ROCCC incorporates several powerful parallelizing transformations targeted towards code generation for FPGAs and can achieve performance comparable to hand-coded VHDL. We have demonstrated speedups r...
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