The Central Trigger System (CTS) for the HADES Experiment

During the last year, the HADES detector setup has been improved in order to achieve several goals, in particular to enhance the capability of the readout electronics [1] [2] (up to 10 events/s). This is required to enable HADES to cope with heavy ion beams at SIS18 and later at the SIS100 at FAIR. Here, one of the major changes of the DAQ upgrade was the replacement of the copper-based cables by high speed optical transmission based media. In this context, the new CTS (Fig. 1) board has been developed. The basic requirement for the CTS hardware is that it has to take the signals coming from several detectors, the TOF (6 inputs), RPC (6) and signals from START (8), VETO (8) detectors and other physical triggers PT (8) to combine them into one trigger signal based on adjustable algorithms like multiplicities and vetos. To enable the above-mentioned features the CTS was equipped with two FPGAs. The first one (Lattice SCM40) is used for the trigger logic, the second one (Lattice ECP2M100) for the standard HADES DAQ operations. The latter FPGA is required for a new dedicated network protocol (TRBNet [4]). The connectivity is provided by four 2Gbit/s optical connections, four 34 pin connectors for detector signals, three 34 pin connectors to send reference time, one 34 pin connector for general purpose and a high data-rate connector to the TRBv2 [3] (on the back of the board). The TRBv2 is needed also for the power supply.