Exploiting Active CMP-based Devices in System Area Networks

We explore the possibility of exploiting the computing power of chip-multiprocessor-based network interface controllers and switches in a system area network environment. We use stream processing applications as case studies to show that combining the compute-power of the host processor and a CMP-based NIC with 4 CPU cores can achieve speedup up to 1.30 even with the NIC running at one tenth the speed of the host processor. We also emphasize that a workload balance between the host CPU and the NIC CPUs is the key to achieving maximum speedup. With detailed simulation, we explore the effects of different NIC memory hierarchies on offloaded application performance. In addition, we propose the idea of two-level active I/O systems with both CMP-based NICs and CMP-based switches, and demonstrate that they can achieve even better performance than a system with active NICs or active switches alone.