Exploration and Design of Sar Logic for Low Power High Speed Sar Adc

Analog-to-digital converters (ADCs) are key design blocks in modern microelectronic digital communication systems. An analog?to?digital converter (ADC) acts as a bridge between the analog and digital worlds. It is a necessary component whenever data from the analog domain, through sensors or transducers, should be digitally processed or when transmitting data between chips through either long-range wireless radio links or high-speed transmission between chips on the same printed circuit board. With the continued proliferation of mixed analog and digital VLSI systems supporting diverse chip functionalities, the need for small sized, low-power and high-speed analog-to-digital converters using conventional CMOS process has increased. Moreover, nowadays power dissipation has become a key performance to be considered in analog designs, especially in those developed for portable devices. Various examples of ADC applications can be found in data acquisition systems, measurement systems and digital communication systems also imaging, instrumentation systems. Hence, we have considered all the parameters and improved the associated performance significantly reduce the industrial cost of an ADC manufacturing process and design specially power consumption. There is a wide variety of different ADC architectures available depending on the requirements of the application. They can range from high-speed, low resolution flash converters to the high-resolution, low-speed oversampled noise-shaping sigma-delta converters. Among various ADC architectures, we chose to implement a Successive Approximation Register (SAR) ADC that is one of the best suited for low power. We target a resolution of 4-bit and a power consumption of few milli watts. The SAR ADC is implemented in 0.18um CMOS technology with a power supply of 1v.