The Evaluation of a Novel Concurrent-Refresh-Aware DRAM System

The DRAM cell density has been continuously increased as technology scales. The increasing DRAM density requires longer refresh time because more rows need to be protected in a single refresh. Since no memory access is allowed during a refresh, the refresh penalty is no longer trivial and can incur significant performance degradation. To mitigate the refresh penalty, a ConcurrentREfresh-Aware Memory system (CREAM) is proposed in this work so that memory access and refresh can be executed concurrently. The proposed CREAM architecture distinguishes itself with the following key contributions: (1) Under a given DRAM power budget, sub-rank-level refresh (SRLR) is developed to reduce refresh power and the saved power is used to enable concurrent memory access for performance improvement; (2) sub-array-level refresh (SALR) is also devised to effectively lower the probability of the conflict between memory access and refresh; (3) In addition, novel sub-array level refresh scheduling schemes, such as sub-array round-robin and dynamic scheduling, are designed to further improve the performance. The feasibility of CREAM is demonstrated by sophisticated design so that CREAM is fully compatible with JEDEC-DDR standard with negligible hardware overhead and no pin-out increase. The experimental results show that CREAM can be comparable to a “non-refresh” memory. In general, it can improve the performance by 12.9% and 7.1% over the conventional DRAM and the Elastic-Refresh DRAM memory, respectively.