Power Minimization by Simultaneous Dual - Vth Assignment and Gate -
نویسندگان
چکیده
|Gate-sizing is an eeective technique to optimize CMOS circuits for dynamic power dissipation and performance while dual-V th (threshold voltage) CMOS is ideal for leakage power reduction in low voltage circuits. This paper focuses on simultaneous dual-V th assignment and gate-sizing to minimize the total power dissipation while maintaining high performance. An accurate power dissipation model that includes short-circuit, switching, and leakage power is derived and used in our optimization. Results show that more than 20% and 40% power reductions are achievable for circuits at high and low switching activities, respectively, compared to single low-V th CMOS circuits while maintaining performance.
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