Implementation of High Speed Pipelined Distributed Arithmetic Based FIR Filter

In the explosive growth of wireless and networking applications, Digital Signal Processing (DSP) operations are extensively used for characterizing and controlling the discrete input signals. For those DSP operations, Finite Impulse Response (FIR) filter is used to filter the unwanted/noise/distorted signals from the discrete input signals. In this study, design of Pipelined Distributed Arithmetic (DA) based FIR filter is implemented through Very Large Scale Integration (VLSI) System design environment for variable word lengths. In general, Multiplication and Accumulation (MAC) unit is the heart of any digital signal processor. But MAC architectures utilize more hardware resources and consume large delay and power. In order to overcome this problem, multiplierless architecture known as distributed arithmetic multiplication is designed in our work. In this study, we introduce Pipelined DA based FIR filter with the help of Pipelining Registers. To reduce the memory size of DA based multiplication, Look-up Tables (LUTs) are partitioned by using Offset Binary Coding (OBC) technique. Hence speed and power consumption of Pipelined DA based FIR filtering operation is improved than traditional DA based FIR filtering operation, for increasing word length inputs.