Gate Size Optimization for Row-based Layouts
نویسندگان
چکیده
A transistor sizing algorithm for row-based layouts is presented under a improved area model. This algorithm uses convex programming to nd a minimal area circuit for a given delay speci cation. The new area model uses a concept of row heights as opposed to the conventional metric of sum of gate sizes. Results over a number of circuit indicate a signi cant reduction both in the minimum delay achievable and area as compared to TILOS-like optimizer.
منابع مشابه
18th Int'l Symposium on Quality Electronic Design
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