A Fast Combined Decimal Adder/Subtractor
نویسندگان
چکیده
An algorithm for a fast decimal addition is proposed. The addition is performed in two steps. First, the result of addition is produced in a decimal signed-digit format. Second, the decimal signed-digit result is converted into the non-redundant form BCD. The conversion uses a borrow generating scheme based on a parallel-prefix network. Using the flexible features of the decimal signed-digit representation, the proposed decimal addition is changed in order to perform a decimal subtraction. An architectural implementation for the combined decimal addition and subtraction is proposed. The design is evaluated and compared with some decimal adders available in the literature and improved performance is reported.
منابع مشابه
Design and Optimization of Reversible BCD Adder/Subtractor Circuit for Quantum and Nanotechnology Based Systems
Reversible logic circuits have found emerging attention in nanotechnology, quantum computing and low power CMOS designs. In this paper we present a modular synthesis method to realize a reversible Binary Coded Decimal (BCD) adder/subtractor circuit. We use genetic algorithms and don’t care concept to design and optimize all parts of a BCD adder circuit in terms of number of garbage inputs/outpu...
متن کاملEfficient Approaches for Designing Quantum Costs of Various Reversible Gates
Over the last few decades, research in reversible logic has increasingly become very popular and it is gaining greater momentum in the present word. Reversible logic has started finding concert applications in quantum computing, optical computing, nano-technology based system, low-power CMOS design, VLSI design. The principal objective of this work is to argue for quantum implementation of vari...
متن کاملSynthesis and Designing of Reversible Adder/Subtracter Circuits
Reversible logic circuits have emerged as a promising technology having its applications in low power CMOS, Quantum Computing, nanotechnology, and optical computing. Power is the major constraint for any circuit Each circuit demands not only low power, but fast speed. This paper is focused on the efficient design of the full Adder/Subtractor with the help of half adder subtractor with single co...
متن کاملEfficient Multiply-by-3 and Divide-by-3 Algorithms and Their Fast Hardware Implementation
This study presents efficient algorithms for performing multiply-by-3 (3N) and divide-by-3 (N/3) operations with the additions and subtractions, respectively. No multiplications and divisions are needed. Full adder (FA) and full subtractor (FS) can be implemented to realize the N3 and N/3 operations, respectively. For fast hardware implementation, this paper introduces two basic cells UCA and U...
متن کاملPlasmonic Adder/Subtractor Module Based on a Ring Resonator Filter
A four port network adder-subtractor module, for surface plasmon polariton (SPP) waves based on a ring resonator filter is proposed. The functionality of module is achieved by the phase difference manipulation of guided SPPs through different arms connected to the ring resonator. The module is designed using the concepts of a basic two-port device proposed in this paper. It is shown that two po...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید
ثبت ناماگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید
ورودعنوان ژورنال:
- CoRR
دوره abs/cs/0503017 شماره
صفحات -
تاریخ انتشار 2005