A Single Precision Asynchronous Floating Point Multiplier
نویسندگان
چکیده
This paper presents the delay of carry save based multiplier of 65nm technology using Field Programmable Gate Array is in enable mode. Here we present a design of floating point multiplication and that can utilize the decimal carry save addition is reduce path delay and dissipation power. The multiplier can stores a less number of multiplicand uses a decimal carry save addition in the portion of iterative presented in the design. Proposed method has to optimize reduce delay. This paper present a single precision asynchronous floating point multiplier implemented by using VERYLOG Hardware description language.
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