Transceiver for 802.11a Wireless LANs in 0.18μm CMOS

Although attractive as a highly integrated solution, direct conversion architecture suffers from problems such as DC offsets, flicker noise and poor quadrature matching, that are further aggravated by using CMOS technology [1]. Furthermore, the 802.11a standard high bit-rate modes require closely matched I/Q frequency response. To alleviate those limitations, a transceiver topology allowing the use of the companion digital chip for calibration, has been implemented as shown in Fig. 20.2.1. Both transmitter and receiver use direct conversion and employ fully differential signal paths. By adding loop-back switches, the DC offset, TX and RX I/Q gain mismatch and I/Q frequency response can be independently calculated and corrected during the idle time between frames or at power-up.