Clock and Power Distribution Networks for 3-D Integrated Circuits

Global interconnect design for threedimensional integrated circuits is a crucial task. Despite the importance of this task, limited results related to global issues have been presented. Challenges in reliably distributing power, ground, and the clock signal within a multi-plane integrated system are discussed in this paper. The design of two 3-D test circuits addressing these issues is described. Candidate 3-D topologies for both power and clock distribution networks are also presented. Design implications due to the different design approaches are discussed. Experimental and simulation results of the 3-D clock and power distribution architectures, respectively, are provided. Both of the test circuits are fabricated by the 3-D fabrication process developed at MIT Lincoln Laboratories (MITLL). The design of the clock and power distribution networks is discussed. I. CLOCK DISTRIBUTION NETWORKS FOR 3-D ICS Distributing the clock signal in 3-D ICs is a complex and challenging task as sequential elements synchronized by the same clock signal can be located on multiple planes [1]. In 2-D circuits, symmetric interconnect structures, such as Hand X-trees, are widely utilized to distribute the clock signal across a circuit [2]. An extension of an H-tree to three dimensions does not guarantee equidistant interconnect paths from the root to the leaves of the tree. The impedance of the TSVs can increase the time for the clock signal to arrive at the leaves of the tree on specific planes as compared to the time for the clock signal to arrive at the leaves of the tree located on the same plane as the clock driver [3]. Consequently, asymmetric topologies can be potential candidates for distributing the clock signal in a 3-D integrated system. Another fundamental issue in the design of clock distribution networks is low power consumption, since the clock network dissipates a significant portion of the total power consumed by a synchronous circuit [2]. This demand is stricter for 3-D ICs due to the increased power density and related thermal concerns. A test circuit investigating the distribution of the clock signal has been recently designed. The test circuit is fabricated by the MITLL process which is a fully depleted silicon-on-insulator process (FDSOI). The minimum feature size of the devices in this test circuit is 180 nm, with one polysilicon layer and three metal layers interconnecting the devices on each wafer. The dimensions of the TSVs in this test circuit are 1.75 μm × 1.75 μm [5]. Each block contains about 30,000 transistors and includes the same logic circuit but implements a different clock distribution architecture. The function of the logic circuit common to the three blocks is to emulate different switching patterns and load conditions for the clock distribution networks under investigation. Random switching patterns are generated in each block by combining pseudorandom number generators and several groups of four-bit counters that switch current loads over different time intervals. Each of the three blocks includes a different clock distribution structure, which are schematically illustrated in Fig. 1. The dashed lines depict vertical interconnects implemented by TSVs. These architectures combine different topologies, such as H-trees, rings, and meshes [2]. The fabricated 3-D test circuit is illustrated in Fig. 2. The highest operational frequency is 1.4 GHz. Clock skew measurements indicate that the topology in Fig. 1a produces, on average, the lowest skew as compared to the other two topologies. The clock skew among the planes is greater for the local mesh topology (see Fig. 1b) as compared to the H-tree topology, primarily due to the unbalanced clock load for certain local meshes. Alternatively, the clock distribution network that includes the global rings exhibits the highest clock skew among all topologies due to the greater difference in distance that the clock signal traverses on each plane [7]. 1st plane 2nd plane 3rd plane 1st plane 2nd plane 3rd plane local clock networks 1st plane 2nd plane 3rd plane (a) (b)