Energy Efficient Branch Prediction

Energy efficiency is of the utmost importance in modern high-performance em-bedded processor design. As the number of transistors on a chip continues to in-crease each year, and processor logic becomes ever more complex, the dynamicswitching power cost of running such processors increases. The continual progres-sion in fabrication processes brings a reduction in the feature size of the transistorstructures on chips with each new technology generation. This reduction in sizeincreases the significance of leakage power (a constant drain that is proportional tothe number of transistors). Particularly in embedded devices, the proportion of anelectronic product’s power budget accounted for by the CPU is significant (oftenas much as 50%).Dynamic branch prediction is a hardware mechanism used to forecast the di-rection, and target address, of branch instructions. This is essential to high per-formance pipelined and superscalar processors, where the direction and target ofbranches is not computed until several stages into the pipeline. Accurate branchprediction also acts to increase energy efficiency by reducing the amount of timespent executing mis-speculated instructions. ‘Stalling’ is no longer a sensible op-tion when the significance of static power dissipation is considered. Dynamicbranch prediction logic typically accounts for over 10% of a processor’s globalpower dissipation, making it an obvious target for energy optimisation.Previous approaches at increasing the energy efficiency of dynamic branch pre-diction logic has focused on either fully dynamic or fully static techniques. Dy-namic techniques include the introduction of a new cache-like structure that candecide whether branch prediction logic should be accessed for a given branch, andstatic techniques tend to focus on scheduling around branch instructions so that aprediction is not needed (or the branch is removed completely).This dissertation explores a method of combining static techniques and pro-filing information with simple hardware support in order to reduce the number ofaccesses made to a branch predictor. The local delay region is used on uncondi-tional absolute branches to avoid prediction, and, for most other branches, AdaptiveBranch Bias Measurement (through profiling) is used to assign a static predictionthat is as accurate as a dynamic prediction for that branch. This information isrepresented as two hint-bits in branch instructions, and then interpreted by simplehardware logic that bypasses both the lookup and update phases for appropriatebranches.The global processor power saving that can be achieved by this Combined Al-gorithm is around 6% on the experimental architectures shown. These architecturesare based upon real contemporary embedded architecture specifications. The introduction of the Combined Algorithm also significantly reduces the exe-cution time of programs on Multiple Instruction Issue processors. This is attributedto the increase achieved in global prediction accuracy.