Integrated Yield Management

As integrated circuit fabrication processes continue to increase in complexity, it has been determined that data collection, retention, and retrieval rates will continue to increase at an alarming rate. At future technology nodes, the time required to source manufacturing problems must at least remain constant to maintain anticipated productivity. Strategies and software methods for integrated yield management (IYM) have been identified as critical for maintaining this productivity. IYM must use integrated circuit design, visible defect, parametric, and functional test data to recognize process trends and excursions so that yield-detracting mechanisms can be rapidly identified and corrected. IYM will require a merging of the various data sources that are maintained throughout the fabrication environment. The availability of multiple data sources and the evolution of automated analysis techniques such as automatic defect classification (ADC) and spatial signature analysis (SSA) are providing mechanisms to convert basic defect, parametric, and electrical data into useful prediction and control information. In this paper we will discuss the current trends towards data management technology integration and suggest new directions for future IYM strategies.