Low-Power Reduced Transistor Image Sensor

An image sensor comprising an array of 128 by 50 super pixels, column parallel current conveyors and global difference double sampling (DDS) unit is presented. The super pixel consists of: a reset transistor, a readout transistor, four transfer transistors and four photodiodes. The photo pixel address switch is placed outside the pixel, effectively implementing 1.5 transistors per pixel using a sharing scheme of the readout and reset transistor. The column FPN of 0.43% from saturated level and SNR of 43.9 dB is measured. The total power consumption is 5 mW at 30 frame/s. Disciplines Electrical and Computer Engineering | Engineering Comments Suggested Citation: Gruev, V., Yang, Z. and Van der Spiegel, J. (2009). "Low-power reduced transistor image sensor." Electronic Letters Vol. 45(15). ©2009 The Institute of Engineering and Technology. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the The Institute of Engineering and Technology. This journal article is available at ScholarlyCommons: http://repository.upenn.edu/ese_papers/581 Low-power reduced transistor image sensor V. Gruev, Z. Yang and J. Van der Spiegel An image sensor comprising an array of 128 by 50 super pixels, column parallel current conveyors and global difference double sampling (DDS) unit is presented. The super pixel consists of: a reset transistor, a readout transistor, four transfer transistors and four photodiodes. The photo pixel address switch is placed outside the pixel, effectively implementing 1.5 transistors per pixel using a sharing scheme of the readout and reset transistor. The column FPN of 0.43% from saturated level and SNR of 43.9 dB is measured. The total power consumption is 5 mW at 30 frame/s. Introduction: Low-power CMOS image sensors are used in various applications, including cell phones, security cameras and automotive cameras. Consumer demands for high pixel count imaging sensors have set trends for small pixel pitch sensors, high signal-to-noise ratios, high dynamic range and better colour replication of the imaged scene, among others. State-of-the-art CMOS imaging sensors are based on the voltage mode three-transistor active pixel sensor paradigm [1]. The introduction of correlated double sampling, i.e. focal plane noise suppression, pinned photodiode and low power consumption, has enabled CMOS imaging sensors to close the performance gap when compared to CCD image sensors. Current mode CMOS image sensors have provided an alternative for low power imaging applications. Some of the strongholds for current mode imaging sensors have higher frame rates than voltage mode counterparts [2] and information extraction at the sensory level [3, 4]. The main limiting factors in current mode image sensors have been low image quality owing to the large fixed pattern noise (FPN) and large temporal noise. This Letter presents a low-power linear current mode image sensor using 1.5 transistors per pixel. The reduced number of transistors per pixel is due to two factors; first, the address switch transistor is eliminated from the pixel and the access of individual pixels is controlled via manipulating the drain and gate voltages of the in-pixel readout transistor; and secondly, four photodiodes share common reset and readout transistors via four transfer transistors. This new pixel architecture allows for smaller pixel pitch owing to the elimination of the switch transistor and access line. The elimination of the access switch also allows for higher linearity between the output photocurrent and the integrated photo voltage and higher SNR figure compared to 3-T current mode APS. Measurements from the image sensors are presented in this Letter. Vreset control register transfer control register