Design and Evaluation of a Distributed Cache Architecture with Prediction
نویسنده
چکیده
We propose a secondary cache architecture that combines a predictive fetch strategy with a distributed cache to build a high performance memory system. The cache is partitioned into smaller units and distributed evenly in the main memory space. The architecture offers high bandwidth between the cache and the DRAM memory. A hardware prediction scheme is used to prefetch data into the cache and hide the high DRAM latency. The prediction scheme does not rely on any predetermined data access patterns and is completely transparent to the user. Simulation of our architecture on a set of benchmark programs showed a 40%-90% improvement in the effective memory access time when compared to traditional caching.
منابع مشابه
Distributed Prefetch-bu er/Cache Design for High Performance Memory Systems
Microprocessor execution speeds are improving at a rate of 50%-80% per year while DRAM access times are improving at a much lower rate of 5%-10% per year. Computer systems are rapidly approaching the point at which overall system performance is determined not by the speed of the CPU but by the memory system speed. We present a high performance memory system architecture that overcomes the growi...
متن کاملAn evaluation of factors affecting the quality of life in low-income housing environments
Housing is the second need after food for human beings. Since the housing crisis began with the increase in population, respective governments were forced to construct houses for a large number of families. Ignoring the qualitative aspects of these houses has caused social and cultural harm. Therefore, designers need to pay more attention to the quality of housing and living environments. The m...
متن کاملQuantitative evaluation of software security: an approach based on UML/SecAM and evidence theory
Quantitative and model-based prediction of security in the architecture design stage facilitates early detection of design faults hence reducing modification costs in subsequent stages of software life cycle. However, an important question arises with respect to the accuracy of input parameters. In practice, security parameters can rarely be estimated accurately due to the lack of sufficient kn...
متن کاملHybrid Shared-aware Cache Coherence Transition Strategy
Chip-multiprocessors have played a significant role in real parallel computer architecture design. For integrating tens of cores into a chip, designs tend towards with physically distributed last level caches. This naturally results in a Non-Uniform Cache Access design, where on-chip access latencies depend on the physical distances between requesting cores and home cores where the data is cach...
متن کامل