Formal Extraction of Memorizing Elements for Sequential VHDL Synthesis
نویسندگان
چکیده
In this paper we present a method for latches and flip flops recognition within VHDL descriptions of hardware systems. Due to the simulation based semantics of VHDL, the existing synthesis tools rely on explicit templates to guarantee memorizing element inference. The approach proposed here is based on a formal representation of VHDL in terms of Interpreted Petri Nets (IPN). After the compilation of the description, a Petri Net preserving the simulation semantic is build. In order to simplify the formal recognition of the memorizing elements appearing in the description, the Petri net is reduced to a unique minimal form. Ultimately a set of equations can be extracted, and a formal analysis is performed on all cyclic VHDL symbol assignments. This methodology has been implemented and is illustrated on a representative set of simple VHDL descriptions.
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