Macromodeling CMOS circuits for timing simulation

A macromodeling and timing simulation technique is presented that allows fast, accurate delay calculations for CMOS circuits. This method is well suited for delay calculations of regular structure VLSI circuits, as well as circuits designed from standard cell libraries. Timing models for both logic gate and transmission gate circuit forms are developed. For logic gates, output transition time and delay time are functions of input transition time and load impedance. Effective resistances for conducting transmission gates and switching transmission gates are functions of input transition time and load capacitance. Transmission gate circuits are then modeled as equivalent RC circuits. Separate waveform models and delay calculation methods exist for both types of circuit forms, with an interface to enable the use of both methods in the same simulation. An experimental event-driven simulator was developed to test the accuracy of the macromodels and to estimate improvements in execution time with respect to SPICE. Typical delay times were within 5% for logic gate circuits and 10% for transmission gate circuits when compared with SPICE. The execution time of the experimental simulator was over two orders of magnitude faster than SPICE. Thesis Supervisor: Jonathan Allen Title: Professor of Electrical Engineering and Computer Science