A 5 GHz DIGITALLY CONTROLLED SYNTHESIZER

By Bill Hamon, M.S. Washington State University MAY 2009 Chair: George S. La Rue This thesis presents the implementation of a self-calibrating low-power Digitally Controlled Synthesizer (DCS) operating at 5 GHz in the IBM 90nm process. The DCS has high tolerance to device and process variations because of its mostly digital design. It provides an extremely wide tuning range with fine resolution. The DCS also has low power consumption and a small layout area. A novel time-to-delay accumulator is used that prevents the need to propagate the carries of a digital adder using two separate delay lines. A 5GHz three bit Johnson counter is described and its use as a frequency divider. A second 10-bit, 5 GHz synchronous counter using complementary logic is also described. The 24-bit time-to-delay accumulator provides 300 Hz frequency resolution and incorporates single-event upset (SEU) mitigation circuitry. The use of Reverse Body Biasing is also discussed to reduce the effects of Total Ionizing Dose (TID) radiation.