Natural language for hardware verification: semantic interpretation and model checking

Our system allows the formal verification of digital circuits using specifications expressed in English. Verification is carried out by the SMV model checker program [McM92]. SMV requires specifications to be written in the temporal logic CTL (computation tree logic). SMV’s model checking algorithm carries out inference over CTL formulas, with respect to a formal representation of a circuit. The system can turn English sentences into CTL formulas, allowing natural language specifications to be used. A parser for English, returning general-purpose semantic representations, is allied with a convertor from these representations to CTL. The convertor is integrated with the SMV model checker, so that inferential information may be used during semantic interpretation. The result exemplifies an interesting class of natural language understanding systems where the target is a specialised reasoning engine (as opposed, say, to a database). The semantic interpretation process exploits this engine, and the application as a whole delivers increased access to a significant industrial technique. A web interface is available at http://www.ltg.ed.ac.uk/prosper/.