A configurable Classification Engine for Polymorphous Chip Architecture

The ever-increasing demands for bandwidth requirement, faster IP forwarding, efficient and effective firewall and flexible differentiated services has resulted in the evolution of sophisticated Network Processor Units (NPUs). We describe a novel approach to implement a pipelined, configurable IPv6 and IPv4 coprocessor for a Network Processor Unit. The coprocessor is capable of providing Forwarding, Firewall and Differentiated Services. We use trie based algorithmic approach for the implementation of the design and extend it by using a morphable data path. The pipelined architecture provides significant improvement in the lookups and updates. The SRAM contains preprocessed IP addresses for forwarding and rules for Diffserv and Firewall engines. Our design scales well with the number entries. The SRAM with preprocessed rules is coupled to the engine with a bus and results in a throughput of 28 Million look up per second for an ASIC implementation and an update time of 8ms, this results in an update rate of 125 entries per second.