FPGA based hardware acceleration for elliptic curve public key cryptosystems

VHDL model descriptions can be processed by synthesis tools in order to derive a netlist of basic logic elements, which can then be fed into place and route tools. Based on this design flow Register Transfer Level (RTL) descriptions have proven to be well suited to efficiently design integrated circuits. In addition to using commercial synthesis tools, there is a lot of potential for application specific model generators, which produce an RTL description from a more abstract rule set. The RTL abstraction level is a good choice when aiming at synthesizable models which have to be independent from the utilized synthesis tool. In 1999 an IEEE Standard [10] was drafted which defines a rule set for RTL synthesis. RTL is characterized by functional blocks, such as registers, memory units or ALUs, and control logic. The latter is based on clocked state transitions. This abstraction level is well-suited for synchronous designs with a clear functionality and hard chipsize or performance constraints. Designers have a good chance to add manual optimizations, and complexity can be managed by a hierarchical design. The Algorithmic Level is defined with multi-cycle operations in mind. While each control step