design and synthesis of high speed low power signed digit adders

Design and Synthesis of High Speed Low Power Signed Digit Adders

Signed digit (SD) number systems provide the possibility of constant-time addition, where inter-digit carry propagation is eliminated. Such carry-free addition is primarily a three-step process; adding the equally weighted SDs to form the primary sum digits, decomposing the latter to interim sum digits and transfer digits, which commonly belong to {–1, 0, 1}, and finally adding the tra...

Design of High-Speed Low-Power Parallel-Prefix VLSI Adders

Parallel-prefix adders offer a highly-efficient solution to the binary addition problem. Several parallel-prefix adder topologies have been presented that exhibit various area and delay characteristics. However, no methodology has been reported so far that directly aims to the reduction of switching activity of the carry-computation unit. In this paper by reformulating the carry equations, we i...

Fast Signed-Digit Multi-operand Decimal Adders

Decimal arithmetic is desirable for high precision requirements of many financial, industrial and scientific applications. Furthermore, hardware support for decimal arithmetic has gained momentum with IEEE 7542008, which standardized decimal floating-point. This paper presents a new architecture for two operand and multi-operand signed-digit decimal addition. Signed-digit architectures are adva...

A Low Power High Speed Adders using MTCMOS Technique

Addition is the most basic arithmetic operation and adder is the most fundamental arithmetic component of the processor. Two important attributes of all digital circuits, for most applications are maximizing speed and minimizing power consumption. The speed of different modules used in the design will dominate the overall performance of the system. Depending on the delay and power consumption r...

High Speed Power Efficient Asynchronous Adders

High-Speed and Low-Power Flash ADCs Encoder

This paper presents a high-speed, low-power and low area encoder for implementation of flash ADCs. Key technique for design of this encoder is performed by convert the conventional 1-of-N thermometer code to 2-of-M codes (M = ¾ N). The proposed encoder is composed from two-stage; in the first stage, thermometer code are converted to 2-of-M codes by used 2-input AND and 4-i...