منابع مشابه
Wave Pipelined VLSI Architecture for a Viterbi Decoder Using Self Reset Logic with 0.65nm Technology
In 3G mobile terminals the Viterbi Decoder consumes approximately one third of the power consumption of a base band mobile transceiver. Viterbi decoders employed in digital wireless communications are complex and dissipate large power. A low power Viterbi decoder is designed in circuit level using self reset logic and wave pipelining technique is implemented for high speed operation. The Viterb...
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1. This paper presents a novel pseudo 4 phase dual rail protocol with self reset logic suited for high speed asynchronous applications. The traditional 4 phase dual rail requires the input to be of alternating valid and empty cycles. However the proposed pseudo 4 phase involves continuous stream of valid data without a separate empty cycle. The empty phase is generated internally so that the ne...
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This paper presents “surfing,” a novel variation of wave pipelining. In previous wave pipelined designs, timing uncertainty grows monotonically as data propagates through gates and other logic elements. Our designs propagate a timing pulse along with the data values, and our logic elements have delays that decrease in the presence of the pulse. This produces a “surfing” effect wherein events ar...
متن کاملHigh-Performance CMOS System Design Using Wave Pipelining
Wave pipelining, or maximum rate pipelining, is a circuit design technique that allows digital synchronous systems to be clocked at rates higher than can be achieved with conventional pipelining techniques. It relies on the predictable nite signal propagation delay through combinational logic for virtual data storage. Wave pipelining of combinational circuits has been shown to achieve clock rat...
متن کاملSome experiments about wave pipelining on FPGA's
Wave pipelining offers a unique combination of high speed, low latency, and moderate power consumption. The construction of wave pipelines is benefited by the use of gates and buffers with data-independent delays and the knowledge of the interconnection delays. These two features are present in several SRAM-based field programmable gate arrays (FPGA’s): look-up tables (LUT’s) allow the designer...
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ژورنال
عنوان ژورنال: VLSI Design
سال: 2008
ISSN: 1065-514X,1563-5171
DOI: 10.1155/2008/738983