Wave-pipelined multiplexed (WPM) routing for gigascale integration (GSI)

Throughput-Centric Wave-Pipelined Interconnect Circuits for Gigascale Integration

A Stochastic Wire-Length Distribution for Gigascale Integration (GSI)—Part I: Derivation and Validation

Based on Rent’s Rule, a well-established empirical relationship, a rigorous derivation of a complete wire-length distribution for on-chip random logic networks is performed. This distribution is compared to actual wire-length distributions for modern microprocessors, and a methodology to calculate the wire-length distribution for future gigascale integration (GSI) products is proposed.

Exploring Microprocessor Architectures for Gigascale Integration

As VLSI advances towards billions of fast transistors on a chip (Gigascale Integration, or GSI), it is becoming clear that interconnect issues will dominate. Conventional uniprocessor architectures, developed in an era when interconnect was largely ignored, may be incompatible with this technology. This paper presents a quantitative exploration of architectural alternatives for gigascale techno...

Atlas: a Dynamically Parallelizing Chip-multiprocessor for Gigascale Integration

Single-chip multiprocessors are an important research direction for future microprocessors. The stigma of this approach is that many important applications cannot be automatically parallelized. This chapter presents a single-chip multiprocessor that engages aggressive speculation techniques to enable dynamic parallelization of irregular, sequential binaries. Thread speculation (multiscalar exec...

A Multizone Pipelined Cache for IP Routing

Caching recently referenced IP addresses and their forwarding information is an effective strategy to increase routing lookup speed. This paper proposes a multizone non-blocking pipelined cache for IP routing lookup that achieves lower miss rates compared to previously reported IP caches. The twostage pipeline design provides a half-prefix half-full address cache and reduces the cache power con...