VLSI CIRCUIT OPTIMIZATION FOR THE 8051 MCU

نویسندگان
چکیده

برای دانلود باید عضویت طلایی داشته باشید

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

VLSI Implementation of 8051 MCU with Decoupling Capacitor for IC-EMC

In recent years, several new methods for IC-level electromagnetic compatibility (EMC) testing have been introduced. Therefore, a handy vehicle for IC-EMC testing is required to validate the effectiveness of the new IC-EMC testing methods. This paper proposes an 8051 MCU for IC-EMC testing platform with in-system programming (ISP) and decoupling capacitor (decap) functions. In order to reduce th...

متن کامل

Multi Objective Inclined Planes System Optimization Algorithm for VLSI Circuit Partitioning

In this paper multi objective optimization problem for partitioning process of VLSI circuit optimization is solved using IPO algorithm. The methodology used in this paper is based upon the dynamic of sliding motion along a frictionless inclined plane. In this work, modules and elements of the circuit are divided into two smaller parts (components) in order to minimize the cutsize and area imbal...

متن کامل

VLSI Circuit Performance Optimization by Geometric Programming

Delay of VLSI circuit components can be controlled by varying their sizes. In other words, performance of VLSI circuits can be optimized by changing the sizes of the circuit components. In this paper, we define a special type of geometric program called unary geometric program. We show that under the Elmore delay model, several commonly used formulations of the circuit component sizing problem ...

متن کامل

Timing and area optimization for standard-cell VLSI circuit design

A standard cell library typically contains several versions of any given gate type, each of which has a di erent gate size. We consider the problem of choosing optimal gate sizes from the library to minimize a cost function (such as total circuit area) while meeting the timing constraints imposed on the circuit. After presenting an e cient algorithm for combinational circuits, we examine the pr...

متن کامل

Performance Optimization of Nonlinear VLSI Interconnect Circuit using Schmitt Trigger

Chip Interconnect delay and power is a primary criterion in the design of an Integrated Circuit because of its close connection to the speed of IC. Interconnect Buffers in VLSI circuits is the most widespread procedure used to decrease power and delay but they outcome in high Delay and power dissipation, thereby degrading the performance (i.e.) operating speed of an integrated circuit. Use of b...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

ژورنال

عنوان ژورنال: International Journal of Technology

سال: 2018

ISSN: 2087-2100,2086-9614

DOI: 10.14716/ijtech.v9i1.798