Two phase clocked subthreshold adiabatic logic circuit
نویسندگان
چکیده
منابع مشابه
Two Phase Clocked Adiabatic Static Logic Circuit: A Proposal for Digital Low Power Applications
This paper proposes a new quasi adiabatic logic family that uses two complementary pulsed supply clock for digital low power applications such as sensors. The proposed two-phase adiabatic static CMOS logic circuit (2PASCL) has switching activity that is lower than dynamic logic and can be directly derived from static CMOS circuits. We have done a SPICE simulation on the chain of four 2PASCL inv...
متن کاملTwo Phase Clocked Adiabatic Static CMOS Logic and its Logic Family
This paper proposes a two-phase clocked adiabatic static CMOS logic (2PASCL) circuit that utilizes the principles of adiabatic switching and energy recovery. The low-power 2PASCL circuit uses two complementary split-level sinusoidal power supply clocks whose height is equal to Vdd. It can be directly derived from static CMOS circuits. By removing the diode from the charging path, higher output ...
متن کاملLow-Power 4×4-Bit Array Two-Phase Clocked Adiabatic Static CMOS Logic Multiplier
The present study evaluates four designs of XOR using our previously reported two-phase clocked adiabatic static CMOS logic (2PASCL) circuit techniques. 2PASCL XOR, which demonstrates the lowest power dissipation, is used for a 4ˆ4-bit array 2PASCL multiplier. Based on simulation results obtained using 0.18 —m standard CMOS technology, at transition frequencies of 1 to 100 MHz, the 4ˆ4-bit arra...
متن کاملDesign of Low Power Barrel Shifter and Rotator Using Two Phase Clocked Adiabatic Static Cmos Logic
This paper presents low power operation of barrel shifter and rotator which are designed and simulated in 2 phase clocked adiabatic static CMOS logic. The power consumption of the circuits is compared with that of static CMOS logic. A barrel logic right shifter, a right rotator and shift/rotator are simulated in 45nm CMOS process technology. A mux based design is used for all the above circuits...
متن کامل4×4-bit array two phase clocked adiabatic static CMOS logic multiplier with new XOR
This paper presents the simulation results of a 4ˆ4-bit array two phase clocked adiabatic static CMOS logic (2PASCL) multiplier using 0.18 —m standard CMOS technology. We also propose a new design of 2PASCL XOR which reduces the number of transistors as well as the power consumption. Analytical method to compare the lower current flow in adiabatic circuit is also presented. At transition freque...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
ژورنال
عنوان ژورنال: IEICE Electronics Express
سال: 2015
ISSN: 1349-2543
DOI: 10.1587/elex.12.20150695