Triple Metal Surrounding Gate Junctionless Tunnel FET Based 6T SRAM Design for Low Leakage Memory System
نویسندگان
چکیده
The promising capability of Triple Material Surrounding Gate Junctionless Tunnel FET (TMSG – JL TFET) based 6 T SRAM structure is demonstrated by employing Germanium (Ge) and High-K gate dielectric material. high K insulation guarantees the proposed device to be used in low leakage memory systems. corresponding analytical model developed extract various parameters such as surface potential, electric field threshold voltage. results yield minimization hot carrier effects at drain end, when compared conventional Silicon (Si) FETs (TFETs). Further, ambipolar characteristics explored Ge TMS SG TFET design proposed. are with CMOS presented validated using 3D - TCAD ATLAS simulation, which ensures accuracy exactness model.
منابع مشابه
SEU sensitivity of Junctionless Single-Gate SOI MOSFETs-based 6T SRAM cells investigated by 3D TCAD simulation
Article history: Received 25 May 2015 Received in revised form 20 June 2015 Accepted 24 June 2015 Available online xxxx
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ژورنال
عنوان ژورنال: Silicon
سال: 2021
ISSN: ['1876-9918', '1876-990X']
DOI: https://doi.org/10.1007/s12633-021-01075-7