Transient-fault recovery for chip multiprocessors

Fault Tolerance Bandwidth Reduction Techniques for Chip Multiprocessors

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on Power - Efficient Fault Tolerant Micro architecture for Chip Multiprocessors

Relentless scaling of silicon fabrication technology coupled with lower design tolerances are making ICs increasing susceptible to wear-out related permanent faults as well as transient faults. A well known technique for tackling both transient and permanent faults is redundant execution, specifically space redundancy, wherein a program is executed redundantly on different processors, pipelines...

1 OpenMP for Chip Multiprocessors

Modern System-on-Chip (SOC) design shows a clear trend towards integration of multiple processor cores, the SOC System Section of the "International Technology Roadmap for Semiconductors" (http://public.itrs.net/) predicts that the number of processor cores will increase dramatically to match the processing demands of future applications. Providers like Intel, IBM, TI, Motorola, and Cradle have...

Processor allocator for chip multiprocessors

Thread Scheduling for Chip Multiprocessors