Timing-driven via placement heuristics for three-dimensional ICs
نویسندگان
چکیده
منابع مشابه
Timing-driven via placement heuristics for three-dimensional ICs
The dependence of the interconnect delay on the interplane via location in three-dimensional (3-D) ICs is investigated in this paper. The delay of these interconnects can be significantly decreased by optimally placing the interplane vias. The via locations that minimize the propagation delay of two-terminal interconnects consisting of multiple interplane vias under the distributed Elmore delay...
متن کاملTiming-Driven Placement
The placement algorithms presented in the previous chapters mostly focus on minimizing the total wirelength (TWL). Timing-driven placement (TDP) is designed specifically targeting wires on timing critical paths. It shall be noted that a cell is usually connected with two or more cells. Making some targeted nets shorter during placement may sacrifice the wirelengths of other nets that are connec...
متن کاملIncremental Timing Driven Placement
Standard cell layouts may need only slight modifications to meet timing constraints. In these situations, general purpose algorithms, which consider numerous parameters of the layout, may be too time consuming or too coarse to make the changes where needed. This paper presents an incremental timing driven placement algorithm designed to “cleanup” a handful of critical paths in a previously plac...
متن کاملCongestion-Driven Global Placement for Three Dimensional VLSI Circuits
The recent popularity of 3D IC technology stems from its enhanced performance capabilities and reduced wiring length. However, the problem of thermal dissipation is magnified due to the nature of these layered technologies. In this paper, we develop techniques to reduce both the local and global congestions of 3D circuit designs in order to alleviate thermal issues. Our approach consists of two...
متن کاملTiming Driven Genetic Algorithm for Standard-cell Placement
In this paper we present a timing-driven placer for standard-cell IC design. The placement algorithm follows the genetic paradigm. A t early generations, the search is biased toward solutions with superior tarning characteristics. As the algorithm starts converging toward generations with acceptable de lay properties, the objective is dynamically adjusted toward optimizing area and routability....
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
ژورنال
عنوان ژورنال: Integration
سال: 2008
ISSN: 0167-9260
DOI: 10.1016/j.vlsi.2007.11.002