ThunderGP: Resource-Efficient Graph Processing Framework on FPGAs with HLS

FPGA has been an emerging computing infrastructure in datacenters benefiting from fine-grained parallelism, energy efficiency, and reconfigurability. Meanwhile, graph processing attracted tremendous interest data analytics, its performance is increasing demand with the rapid growth of data. Many works have proposed to tackle challenges designing efficient FPGA-based accelerators for processing. However, largely overlooked programmability still requires hardware design expertise sizable development efforts developers. ThunderGP , a high-level synthesis based framework on FPGAs, hence close gap, which developers could enjoy high FPGA-accelerated by writing only few functions no knowledge hardware. adopts gather-apply-scatter model as abstraction various algorithms realizes built-in highly parallel memory-efficient accelerator template. With inputs, automatically explores massive resources multiple super-logic regions modern platforms generate deploy accelerators, well schedule tasks them. Although DRAM-based memory bandwidth bounded, recent (HBM) brings large potentials performance. system bottleneck shifts resource consumption HBM-enabled platforms. Therefore, we further propose improve efficiency utilize more HBM. We conduct evaluation seven common applications 19 graphs. provides 1.9× ∼ 5.2× improvement over state art, whereas HBM-based delivers up speedup state-of-the-art RTL-based approach. This work open sourced GitHub at https://github.com/Xtra-Computing/ThunderGP .