Techniques for Self-Checking Combinational Logic Synthesis

Iterative Combinational Logic Synthesis Techniques Using Spectral Data

Iterative Combinational Logic Synthesis Techniques Using Spectral Data

On the Efficiency of Learning Techniques for Combinational Equivalence Checking

Recursive learning is a general technique for analyzing Boolean problems. In this paper, we evaluate various heuristics for improving the runtime efficiency of this technique when applied to the problem of combinational equivalence checking. All heuristics are evaluated on a set of 29 examples containing the ISCAS benchmarks as well as industrial designs.

Techniques for Estimation of Design Diversity for Combinational Logic Circuits

Design diversity has long been used to protect redundant systems against common-mode failures. The conventional notion of diversity relies on “independent” generation of “different” implementations of the same logic function. This concept is qualitative and does not provide a basis to compare the reliabilities of two diverse systems. In a recent paper, we presented a metric to quantify diversit...

Delay-Reduced Combinational Logic Synthesis using Multiplexers

This paper presents an approach to obtain reduced hardware and/or delay for synthesizing logic functions using multiplexers. Replication of single control line multiplexer is used as the only design unit for defining any logic function specified by minterms. An algorithm is proposed that does exhaustive branching to reduce the number of levels and/or modules required to implement any logic func...