Stochastic Dividers for Low Latency Neural Networks

Due to the low complexity in arithmetic unit design, stochastic computing (SC) has attracted considerable interest implement Artificial Neural Networks (ANNs) for resources-limited applications, because ANNs must usually perform a large number of operations. To attain high computation accuracy an SC-based ANN, extended logic is utilized together with standard SC units and thus, divider required conversion between these representations. However, conventional incurs latency, so limits implementation used applications needing performance. Therefore, there need design fast dividers ANNs. Recent works (e.g., binary searching triple modular redundancy (BS-TMR) based divider) are targeting reduction while keeping same compared traditional design. this still requires $N$ iterations deal notation="LaTeX">$2^{N}$ -bit sequences, thus latency increases proportion sequence length. In paper, decimal TMR (DS-TMR) initially proposed further reduce latency; it only two calculate quotient, regardless Moreover, trade-off hardware also presented. An Multi-Layer Perceptron (MLP) then considered show effectiveness over current designs. Results that when utilizing dividers, MLP achieves lowest classification accuracy; although incurring area increase, overhead due entire MLP. When using as combined metric both product area, power clock cycles, designs shown be superior MLPs (at level accuracy) employing other found technical literature well commonly 32-bit floating point implementation.